36 lines
950 B
VHDL
36 lines
950 B
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY gen_impuls is
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PORT (
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clk : IN STD_LOGIC;
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rst_n : IN STD_LOGIC;
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max : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
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impuls : OUT STD_LOGIC
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);
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END gen_impuls;
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ARCHITECTURE archi OF gen_impuls is
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SIGNAL valeur_interne : STD_LOGIC_VECTOR(28 DOWNTO 0);
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BEGIN
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PROCESS (clk, rst_n)
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begin
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IF rst_n = '0' THEN
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valeur_interne <= (OTHERS => '0');
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else
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IF rising_edge(clk) THEN
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IF valeur_interne = max THEN
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valeur_interne <= (OTHERS => '0');
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-- impuls <= '1';
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else
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-- impuls <= '0';
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valeur_interne <= STD_LOGIC_VECTOR(UNSIGNED(valeur_interne) + 1);
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END IF;
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END IF;
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END IF;
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END PROCESS;
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impuls <= '1' WHEN valeur_interne = max ELSE '0';
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END archi; |