LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY gen_impuls is
    PORT (
        clk : IN STD_LOGIC;
        rst_n : IN STD_LOGIC;
        max : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
        impuls : OUT STD_LOGIC
    );
END gen_impuls;

ARCHITECTURE archi OF gen_impuls is
    SIGNAL valeur_interne : STD_LOGIC_VECTOR(28 DOWNTO 0);
BEGIN
    PROCESS (clk, rst_n)
    begin
        IF rst_n = '0' THEN
            valeur_interne <= (OTHERS => '0');
        else
            IF rising_edge(clk) THEN
                IF valeur_interne = max THEN
                    valeur_interne <= (OTHERS => '0');
                    -- impuls <= '1';
                else
                    -- impuls <= '0';
                    valeur_interne <= STD_LOGIC_VECTOR(UNSIGNED(valeur_interne) + 1);
                END IF;
            END IF;
        END IF;
    END PROCESS;

    impuls <= '1' WHEN valeur_interne = max ELSE '0';

END archi;