26 lines
356 B
VHDL
26 lines
356 B
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY maj3 is
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PORT (
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p : IN STD_LOGIC;
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s : IN STD_LOGIC;
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t : IN STD_LOGIC;
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m : OUT STD_LOGIC;
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n : OUT STD_LOGIC
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);
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END maj3;
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ARCHITECTURE archi OF maj3 is
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SIGNAL result : STD_LOGIC;
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BEGIN
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result <= (t AND s) OR (P AND t) OR (p AND s);
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m <= result;
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n <= NOT(result);
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end archi; |