19 lines
231 B
VHDL
19 lines
231 B
VHDL
LIRABRY ieee;
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USE ieee.std_logic_1166.ALL;
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ENTITY et2 IS
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PORT (
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a : IN STD_LOGIC;
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b : IN STD_LOGIC;
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S : OUT STD_LOGIC
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);
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END et2;
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ARCHITECTURE archi OF et2 IS
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BEGIN
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s <= A AND B;
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END archi; |