82 lines
1.7 KiB
VHDL
82 lines
1.7 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY chrono_complet IS
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PORT (
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clk : IN STD_LOGIC;
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rst_n : IN STD_LOGIC;
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a1, b1, c1, d1, e1, f1, g1, p1 : OUT STD_LOGIC;
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a2, b2, c2, d2, e2, f2, g2, p2 : OUT STD_LOGIC;
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a3, b3, c3, d3, e3, f3, g3, p3 : OUT STD_LOGIC
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);
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END chrono_complet;
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ARCHITECTURE archi OF chrono_complet IS
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COMPONENT chiffre
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PORT (
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clk : IN STD_LOGIC;
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rst_n : IN STD_LOGIC;
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nb_fronts : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
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n_max : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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a : OUT STD_LOGIC;
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b : OUT STD_LOGIC;
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c : OUT STD_LOGIC;
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d : OUT STD_LOGIC;
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e : OUT STD_LOGIC;
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f : OUT STD_LOGIC;
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g : OUT STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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chiffre1 : chiffre
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PORT MAP(
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clk => clk,
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rst_n => rst_n,
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nb_fronts => "11101110011010110010011111111",
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n_max => "0101",
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a => a1,
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b => b1,
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c => c1,
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d => d1,
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e => e1,
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f => f1,
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g => g1
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);
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chiffre2 : chiffre
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PORT MAP(
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clk => clk,
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rst_n => rst_n,
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nb_fronts => "00010111110101111000001111111",
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n_max => "1001",
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a => a2,
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b => b2,
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c => c2,
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d => d2,
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e => e2,
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f => f2,
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g => g2
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);
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chiffre3 : chiffre
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PORT MAP(
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clk => clk,
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rst_n => rst_n,
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nb_fronts => "00000010011000100101100111111",
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n_max => "1001",
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a => a3,
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b => b3,
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c => c3,
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d => d3,
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e => e3,
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f => f3,
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g => g3
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);
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p1 <= '1';
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p2 <= '0';
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p3 <= '1';
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END archi; |