46 lines
847 B
VHDL
46 lines
847 B
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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ENTITY BCD7seg is
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PORT (
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n : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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a : OUT STD_LOGIC;
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b : OUT STD_LOGIC;
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c : OUT STD_LOGIC;
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d : OUT STD_LOGIC;
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e : OUT STD_LOGIC;
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f : OUT STD_LOGIC;
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g : OUT STD_LOGIC
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);
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END BCD7seg;
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ARCHITECTURE archi OF BCD7seg is
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SIGNAL segments : STD_LOGIC_VECTOR(6 DOWNTO 0);
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BEGIN
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WITH n SELECT
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segments <= "0000001" WHEN "0000",
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"1001111" WHEN "0001",
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"0010010" WHEN "0010",
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"0000110" WHEN "0011",
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"1001100" WHEN "0100",
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"0100100" WHEN "0101",
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"0100000" WHEN "0110",
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"0001111" WHEN "0111",
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"0000000" WHEN "1000",
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"0000100" WHEN OTHERS;
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a <= segments(6);
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b <= segments(5);
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c <= segments(4);
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d <= segments(3);
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e <= segments(2);
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f <= segments(1);
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g <= segments(0);
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end archi; |