86 lines
1.9 KiB
VHDL
86 lines
1.9 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY chiffre IS
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PORT (
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clk : IN STD_LOGIC;
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rst_n : IN STD_LOGIC;
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nb_fronts : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
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n_max : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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a : OUT STD_LOGIC;
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b : OUT STD_LOGIC;
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c : OUT STD_LOGIC;
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d : OUT STD_LOGIC;
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e : OUT STD_LOGIC;
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f : OUT STD_LOGIC;
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g : OUT STD_LOGIC
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);
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END chiffre;
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ARCHITECTURE archi OF chiffre IS
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COMPONENT gen_impuls
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PORT (
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clk : IN STD_LOGIC;
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rst_n : IN STD_LOGIC;
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max : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
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impuls : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT compteur_max_ena
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PORT (
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clk : IN STD_LOGIC;
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rst_n : IN STD_LOGIC;
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max : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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ena : IN STD_LOGIC;
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valeur : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT BCD7seg
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PORT (
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n : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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a : OUT STD_LOGIC;
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b : OUT STD_LOGIC;
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c : OUT STD_LOGIC;
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d : OUT STD_LOGIC;
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e : OUT STD_LOGIC;
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f : OUT STD_LOGIC;
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g : OUT STD_LOGIC
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);
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END COMPONENT;
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SIGNAL impulsion : STD_LOGIC;
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SIGNAL nombre : STD_LOGIC_VECTOR(3 DOWNTO 0);
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BEGIN
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gen_impuls_1 : gen_impuls
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PORT MAP(
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clk => clk,
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rst_n => rst_n,
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max => nb_fronts,
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impuls => impulsion
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);
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compteur_max_ena_1 : compteur_max_ena
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PORT MAP(
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clk => clk,
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rst_n => rst_n,
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max => n_max,
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ena => impulsion,
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valeur => nombre
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);
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BCD7seg_1 : BCD7seg
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PORT MAP(
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n => nombre,
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a => a,
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b => b,
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c => c,
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d => d,
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e => e,
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f => f,
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g => g
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);
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END archi; |