LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY maj3 is 
	PORT (
		p : IN STD_LOGIC;
      s : IN STD_LOGIC;
      t : IN STD_LOGIC;
		m : OUT STD_LOGIC;
		n : OUT STD_LOGIC
		);
		
END maj3;

ARCHITECTURE archi OF maj3 is

SIGNAL result : STD_LOGIC;

BEGIN

	result <= (t AND s) OR (P AND t) OR (p AND s);
	
	m <= result;
	n <= NOT(result);

end archi;