First commit

.gitignore

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+
+CITISE1.7z
+
+*.aux
+
+*.log
+
+*.out
+
+*.gz
+
+*.tex
+
+*.toc
+
+*.glg
+
+*.glo
+
+*.ist
+
+*.gls

.stfolder/syncthing-folder-77ec0e.txt

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+# This directory is a Syncthing folder marker.
+# Do not delete.
+
+folderID: zdqey-gdv84
+created: 2025-12-15T19:22:49+01:00

Global/Chartes Graphiques/télécom saint-étienne.svg

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IUT/Auto1/Ascenseur/lift_ctrl.qarlog

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+
+
+******* Archived project restoration attempt on Mon Jan 19 14:58:19 2026
+Source archive file:	/home/noamh/CITISE1/IUT/Auto1/Ascenseur/lift_ctrl.qar
+Archive was extracted into	/home/noamh/CITISE1/IUT/Auto1/Ascenseur/lift_ctrl_restored/
+		 - successfully.

IUT/Auto1/TP/BCD7seg/BCD7seg.vhd

@@ -0,0 +1,46 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+
+ENTITY BCD7seg is 
+	PORT (
+		n : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		a : OUT STD_LOGIC;
+		b : OUT STD_LOGIC;
+		c : OUT STD_LOGIC;
+		d : OUT STD_LOGIC;
+		e : OUT STD_LOGIC;
+		f : OUT STD_LOGIC;
+		g : OUT STD_LOGIC
+		);
+		
+END BCD7seg;
+
+ARCHITECTURE archi OF BCD7seg is
+
+SIGNAL segments : STD_LOGIC_VECTOR(6 DOWNTO 0);
+
+BEGIN
+	
+	WITH n SELECT
+	segments <= "0000001" WHEN "0000",
+					"1001111" WHEN "0001",
+					"0010010" WHEN "0010",
+					"0000110" WHEN "0011",
+					"1001100" WHEN "0100",
+					"0100100" WHEN "0101",
+					"0100000" WHEN "0110",
+					"0001111" WHEN "0111",
+					"0000000" WHEN "1000",
+					"0000100" WHEN OTHERS;
+	
+	a <= segments(6);
+	b <= segments(5);
+	c <= segments(4);
+	d <= segments(3);
+	e <= segments(2);
+	f <= segments(1);
+	g <= segments(0);
+	
+	
+end archi;

IUT/Auto1/TP/chiffre/chiffre.vhd

@@ -0,0 +1,86 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY chiffre IS
+    PORT (
+        clk : IN STD_LOGIC;
+        rst_n : IN STD_LOGIC;
+        nb_fronts : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
+        n_max : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+        a : OUT STD_LOGIC;
+        b : OUT STD_LOGIC;
+        c : OUT STD_LOGIC;
+        d : OUT STD_LOGIC;
+        e : OUT STD_LOGIC;
+        f : OUT STD_LOGIC;
+        g : OUT STD_LOGIC
+    );
+END chiffre;
+
+ARCHITECTURE archi OF chiffre IS
+    COMPONENT gen_impuls
+        PORT (
+            clk : IN STD_LOGIC;
+            rst_n : IN STD_LOGIC;
+            max : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
+            impuls : OUT STD_LOGIC
+        );
+    END COMPONENT;
+
+    COMPONENT compteur_max_ena
+        PORT (
+            clk : IN STD_LOGIC;
+            rst_n : IN STD_LOGIC;
+            max : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+            ena : IN STD_LOGIC;
+            valeur : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+        );
+    END COMPONENT;
+
+    COMPONENT BCD7seg
+        PORT (
+            n : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+            a : OUT STD_LOGIC;
+            b : OUT STD_LOGIC;
+            c : OUT STD_LOGIC;
+            d : OUT STD_LOGIC;
+            e : OUT STD_LOGIC;
+            f : OUT STD_LOGIC;
+            g : OUT STD_LOGIC
+        );
+    END COMPONENT;
+
+    SIGNAL impulsion : STD_LOGIC;
+    SIGNAL nombre : STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+BEGIN
+    gen_impuls_1 : gen_impuls
+    PORT MAP(
+        clk => clk,
+        rst_n => rst_n,
+        max => nb_fronts,
+        impuls => impulsion
+    );
+
+    compteur_max_ena_1 : compteur_max_ena
+    PORT MAP(
+        clk => clk,
+        rst_n => rst_n,
+        max => n_max,
+        ena => impulsion,
+        valeur => nombre
+    );
+
+    BCD7seg_1 : BCD7seg
+    PORT MAP(
+        n => nombre,
+        a => a,
+        b => b,
+        c => c,
+        d => d,
+        e => e,
+        f => f,
+        g => g
+    );
+END archi;

IUT/Auto1/TP/chrono_complet/chrono_complet.vhd

@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY chrono_complet IS
+    PORT (
+        clk : IN STD_LOGIC;
+        rst_n : IN STD_LOGIC;
+        a1, b1, c1, d1, e1, f1, g1, p1 : OUT STD_LOGIC;
+        a2, b2, c2, d2, e2, f2, g2, p2 : OUT STD_LOGIC;
+        a3, b3, c3, d3, e3, f3, g3, p3 : OUT STD_LOGIC
+    );
+END chrono_complet;
+
+ARCHITECTURE archi OF chrono_complet IS
+    COMPONENT chiffre
+        PORT (
+            clk : IN STD_LOGIC;
+            rst_n : IN STD_LOGIC;
+            nb_fronts : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
+            n_max : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+            a : OUT STD_LOGIC;
+            b : OUT STD_LOGIC;
+            c : OUT STD_LOGIC;
+            d : OUT STD_LOGIC;
+            e : OUT STD_LOGIC;
+            f : OUT STD_LOGIC;
+            g : OUT STD_LOGIC
+        );
+    END COMPONENT;
+
+BEGIN
+    chiffre1 : chiffre
+    PORT MAP(
+        clk => clk,
+        rst_n => rst_n,
+        nb_fronts => "11101110011010110010011111111",
+        n_max => "0101",
+        a => a1,
+        b => b1,
+        c => c1,
+        d => d1,
+        e => e1,
+        f => f1,
+        g => g1
+    );
+
+    chiffre2 : chiffre
+    PORT MAP(
+        clk => clk,
+        rst_n => rst_n,
+        nb_fronts => "00010111110101111000001111111",
+        n_max => "1001",
+        a => a2,
+        b => b2,
+        c => c2,
+        d => d2,
+        e => e2,
+        f => f2,
+        g => g2
+    );
+
+    chiffre3 : chiffre
+    PORT MAP(
+        clk => clk,
+        rst_n => rst_n,
+        nb_fronts => "00000010011000100101100111111",
+        n_max => "1001",
+        a => a3,
+        b => b3,
+        c => c3,
+        d => d3,
+        e => e3,
+        f => f3,
+        g => g3
+    );
+
+    p1 <= '1';
+    p2 <= '0';
+    p3 <= '1';
+
+END archi;

IUT/Auto1/TP/chrono_secondes/chrono_secondes.vhd

@@ -0,0 +1,86 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY chiffre IS
+    PORT (
+        clk : IN STD_LOGIC;
+        rst_n : IN STD_LOGIC;
+        nb_fronts : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
+        n_max : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+        a : OUT STD_LOGIC;
+        b : OUT STD_LOGIC;
+        c : OUT STD_LOGIC;
+        d : OUT STD_LOGIC;
+        e : OUT STD_LOGIC;
+        f : OUT STD_LOGIC;
+        g : OUT STD_LOGIC
+    );
+END chiffre;
+
+ARCHITECTURE archi OF chiffre IS
+    COMPONENT gen_impuls
+        PORT (
+            clk : IN STD_LOGIC;
+            rst_n : IN STD_LOGIC;
+            max : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
+            impuls : OUT STD_LOGIC
+        );
+    END COMPONENT;
+
+    COMPONENT compteur_max_ena
+        PORT (
+            clk : IN STD_LOGIC;
+            rst_n : IN STD_LOGIC;
+            max : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+            ena : IN STD_LOGIC;
+            valeur : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+        );
+    END COMPONENT;
+
+    COMPONENT BCD7seg
+        PORT (
+            n : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+            a : OUT STD_LOGIC;
+            b : OUT STD_LOGIC;
+            c : OUT STD_LOGIC;
+            d : OUT STD_LOGIC;
+            e : OUT STD_LOGIC;
+            f : OUT STD_LOGIC;
+            g : OUT STD_LOGIC
+        );
+    END COMPONENT;
+
+    SIGNAL impulsion : STD_LOGIC;
+    SIGNAL nombre : STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+BEGIN
+    gen_impuls_1 : gen_impuls
+    PORT MAP(
+        clk => clk,
+        rst_n => rst_n,
+        max => nb_fronts,
+        impuls => impulsion
+    );
+
+    compteur_max_ena_1 : compteur_max_ena
+    PORT MAP(
+        clk => clk,
+        rst_n => rst_n,
+        max => n_max,
+        ena => impulsion,
+        valeur => nombre
+    );
+
+    BCD7seg_1 : BCD7seg
+    PORT MAP(
+        n => nombre,
+        a => a,
+        b => b,
+        c => c,
+        d => d,
+        e => e,
+        f => f,
+        g => g
+    );
+END archi;

IUT/Auto1/TP/compteur/compteur.vhd

@@ -0,0 +1,36 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY compteur is
+    PORT (
+        clk : IN STD_LOGIC;
+        rst_n : IN STD_LOGIC;
+        max : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+        enable : IN STD_LOGIC;
+        valeur : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+    );
+END compteur;
+
+ARCHITECTURE archi OF compteur is
+    SIGNAL valeur_interne : STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+BEGIN
+    PROCESS (clk, rst_n)
+    begin
+        IF rst_n = '0' THEN
+            valeur_interne <= (OTHERS => '0');
+        else
+            IF rising_edge(clk) AND enable = '1' THEN
+                IF valeur_interne = max THEN
+                    valeur_interne <= (OTHERS => '0');
+                else
+                    valeur_interne <= STD_LOGIC_VECTOR(UNSIGNED(valeur_interne) + 1);
+                END IF;
+            END IF;
+        END IF;
+    END PROCESS;
+
+    valeur <= valeur_interne;
+
+END archi;

IUT/Auto1/TP/compteur_max_ena/compteur_max_ena.vhd

@@ -0,0 +1,36 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY compteur_max_ena is
+    PORT (
+        clk : IN STD_LOGIC;
+        rst_n : IN STD_LOGIC;
+        max : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+        ena : IN STD_LOGIC;
+        valeur : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+    );
+END compteur_max_ena;
+
+ARCHITECTURE archi OF compteur_max_ena is
+    SIGNAL valeur_interne : STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+BEGIN
+    PROCESS (clk, rst_n)
+    begin
+        IF rst_n = '0' THEN
+            valeur_interne <= (OTHERS => '0');
+        else
+            IF rising_edge(clk) AND ena = '1' THEN
+                IF valeur_interne = max THEN
+                    valeur_interne <= (OTHERS => '0');
+                else
+                    valeur_interne <= STD_LOGIC_VECTOR(UNSIGNED(valeur_interne) + 1);
+                END IF;
+            END IF;
+        END IF;
+    END PROCESS;
+
+    valeur <= valeur_interne;
+
+END archi;

IUT/Auto1/TP/depassement_niveau/depassement_niveau.vhd

@@ -0,0 +1,21 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY depassement_niveau is 
+	PORT (
+		niveau_liquide : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+  		depassement : OUT STD_LOGIC
+		);
+		
+END depassement_niveau;
+
+ARCHITECTURE archi OF depassement_niveau is
+
+SIGNAL result : STD_LOGIC;
+
+BEGIN
+
+	depassement <= '1' WHEN niveau_liquide > "1010" ELSE '0';
+
+end archi;

IUT/Auto1/TP/et2/et2.vhd

@@ -0,0 +1,19 @@
+LIRABRY ieee;
+USE ieee.std_logic_1166.ALL;
+
+ENTITY et2 IS
+    PORT (
+        a : IN STD_LOGIC;
+        b : IN STD_LOGIC;
+        S : OUT STD_LOGIC
+    );
+
+END et2;
+
+ARCHITECTURE archi OF et2 IS
+
+BEGIN
+
+    s <= A AND B;
+
+END archi;

IUT/Auto1/TP/gen_impuls/gen_impuls.vhd

@@ -0,0 +1,36 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY gen_impuls is
+    PORT (
+        clk : IN STD_LOGIC;
+        rst_n : IN STD_LOGIC;
+        max : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
+        impuls : OUT STD_LOGIC
+    );
+END gen_impuls;
+
+ARCHITECTURE archi OF gen_impuls is
+    SIGNAL valeur_interne : STD_LOGIC_VECTOR(28 DOWNTO 0);
+BEGIN
+    PROCESS (clk, rst_n)
+    begin
+        IF rst_n = '0' THEN
+            valeur_interne <= (OTHERS => '0');
+        else
+            IF rising_edge(clk) THEN
+                IF valeur_interne = max THEN
+                    valeur_interne <= (OTHERS => '0');
+                    -- impuls <= '1';
+                else
+                    -- impuls <= '0';
+                    valeur_interne <= STD_LOGIC_VECTOR(UNSIGNED(valeur_interne) + 1);
+                END IF;
+            END IF;
+        END IF;
+    END PROCESS;
+
+    impuls <= '1' WHEN valeur_interne = max ELSE '0';
+
+END archi;

IUT/Auto1/TP/maj3/maj3.vhd

@@ -0,0 +1,26 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY maj3 is 
+	PORT (
+		p : IN STD_LOGIC;
+      s : IN STD_LOGIC;
+      t : IN STD_LOGIC;
+		m : OUT STD_LOGIC;
+		n : OUT STD_LOGIC
+		);
+		
+END maj3;
+
+ARCHITECTURE archi OF maj3 is
+
+SIGNAL result : STD_LOGIC;
+
+BEGIN
+
+	result <= (t AND s) OR (P AND t) OR (p AND s);
+	
+	m <= result;
+	n <= NOT(result);
+
+end archi;