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Noam Hache
2026-04-08 20:11:20 +02:00
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{
"cSpell.words": [
"PTBD",
"PTBDD"
]
}

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\begin{MintedVerbatim}[commandchars=\\\{\}]
\PYG{c+cm}{/*** PTAD \PYGZhy{} Port A Data Register; 0x00000000 ***/}
\PYG{k}{typedef}\PYG{+w}{ }\PYG{k}{union}\PYG{+w}{ }\PYG{p}{\PYGZob{}}
\PYG{+w}{ }\PYG{n}{byte}\PYG{+w}{ }\PYG{n}{Byte}\PYG{p}{;}
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\end{MintedVerbatim}

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\begin{MintedVerbatim}[commandchars=\\\{\}]
\PYG{+w}{ }\PYG{n}{PTBD}\PYG{+w}{ }\PYG{o}{\PYGZam{}}\PYG{+w}{ }\PYG{l+m+mh}{0x20}
\end{MintedVerbatim}

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\begin{MintedVerbatim}[commandchars=\\\{\}]
\PYG{+w}{ }\PYG{k}{if}\PYG{+w}{ }\PYG{p}{(}\PYG{n}{PTBD\PYGZus{}PTBD4}\PYG{+w}{ }\PYG{o}{==}\PYG{+w}{ }\PYG{l+m+mb}{0b1}\PYG{p}{)}\PYG{+w}{ }\PYG{p}{\PYGZob{}}
\PYG{+w}{ }\PYG{p}{...}
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\begin{MintedVerbatim}[commandchars=\\\{\}]
\PYG{+w}{ }\PYG{k}{extern}\PYG{+w}{ }\PYG{k}{volatile}\PYG{+w}{ }\PYG{n}{PTBDSTR}\PYG{+w}{ }\PYG{n}{\PYGZus{}PTBD}\PYG{+w}{ }\PYG{err}{@}\PYG{l+m+mh}{0x00000002}\PYG{p}{;}
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\end{MintedVerbatim}

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@book{TheCProgrammingLanguage,
author = {Brian W. Kernighan, Dennis M. Ritchie},
title = {Le langage C},
year = {1990}
}

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\@namedef{PYG@tok@mf}{\def\PYG@tc##1{\textcolor[rgb]{0.40,0.40,0.40}{##1}}}
\@namedef{PYG@tok@mh}{\def\PYG@tc##1{\textcolor[rgb]{0.40,0.40,0.40}{##1}}}
\@namedef{PYG@tok@mi}{\def\PYG@tc##1{\textcolor[rgb]{0.40,0.40,0.40}{##1}}}
\@namedef{PYG@tok@il}{\def\PYG@tc##1{\textcolor[rgb]{0.40,0.40,0.40}{##1}}}
\@namedef{PYG@tok@mo}{\def\PYG@tc##1{\textcolor[rgb]{0.40,0.40,0.40}{##1}}}
\@namedef{PYG@tok@ch}{\let\PYG@it=\textit\def\PYG@tc##1{\textcolor[rgb]{0.24,0.48,0.48}{##1}}}
\@namedef{PYG@tok@cm}{\let\PYG@it=\textit\def\PYG@tc##1{\textcolor[rgb]{0.24,0.48,0.48}{##1}}}
\@namedef{PYG@tok@cpf}{\let\PYG@it=\textit\def\PYG@tc##1{\textcolor[rgb]{0.24,0.48,0.48}{##1}}}
\@namedef{PYG@tok@c1}{\let\PYG@it=\textit\def\PYG@tc##1{\textcolor[rgb]{0.24,0.48,0.48}{##1}}}
\@namedef{PYG@tok@cs}{\let\PYG@it=\textit\def\PYG@tc##1{\textcolor[rgb]{0.24,0.48,0.48}{##1}}}
\def\PYGZbs{\char`\\}
\def\PYGZus{\char`\_}
\def\PYGZob{\char`\{}
\def\PYGZcb{\char`\}}
\def\PYGZca{\char`\^}
\def\PYGZam{\char`\&}
\def\PYGZlt{\char`\<}
\def\PYGZgt{\char`\>}
\def\PYGZsh{\char`\#}
\def\PYGZpc{\char`\%}
\def\PYGZdl{\char`\$}
\def\PYGZhy{\char`\-}
\def\PYGZsq{\char`\'}
\def\PYGZdq{\char`\"}
\def\PYGZti{\char`\~}
% for compatibility with earlier versions
\def\PYGZat{@}
\def\PYGZlb{[}
\def\PYGZrb{]}
\makeatother

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OPEN source 0 0 60 39
Source < attributes MARKS off
OPEN assembly 60 0 40 31
Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C
OPEN procedure 0 39 60 17
Procedure < attributes VALUES on,TYPES off
OPEN register 60 31 40 25
Register < attributes FORMAT AUTO,COMPLEMENT None
OPEN memory 60 56 40 22
Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80
OPEN data 0 56 60 22
Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16
OPEN data 0 78 60 22
Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16
OPEN command 60 78 40 22
Command < attributes CACHESIZE 1000
bckcolor 50331647
font 'Courier New' 9 BLACK
AUTOSIZE on
ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory

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[Environment Variables]
GENPATH={Project}Sources;{Compiler}lib\hc08c\device\src;{Compiler}lib\hc08c\device\include;{Compiler}lib\hc08c\device\asm_include;{Compiler}lib\hc08c\src;{Compiler}lib\hc08c\include;{Compiler}lib\hc08c\lib
LIBPATH={Compiler}lib\hc08c\device\include;{Compiler}lib\hc08c\include
OBJPATH={Project}bin
TEXTPATH={Project}bin
ABSPATH={Project}bin
[HI-WAVE]
Target=HCS08FCS
Layout=C_layout.hwl
LoadDialogOptions=RUNANDSTOPAFTERLOAD="main"
MainFrame=2,3,-1,-1,-1,-1,345,107,1785,860
TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806
[HCS08FCS]
CURRENTDEVICE=9S08QG8
CMDFILE0=CMDFILE STARTUP ON ".\cmd\HCS08_Full_Chip_Simulator_startup.cmd"
CMDFILE1=CMDFILE RESET ON ".\cmd\HCS08_Full_Chip_Simulator_reset.cmd"
CMDFILE2=CMDFILE PRELOAD ON ".\cmd\HCS08_Full_Chip_Simulator_preload.cmd"
CMDFILE3=CMDFILE POSTLOAD ON ".\cmd\HCS08_Full_Chip_Simulator_postload.cmd"
SHOWPROT=0
TRACE_ENABLEDISABLESTATE=0
[PEDEBUG]
CURRENTDEVICE=9S08QG8
CURRENTMODE=1
ASK_BEFORE_ERASING_FLASH=1
AUTO_SYNC=1
DO_INIT_PORTS=1
[DEVICE]
CHIPMODE=9S08QG8
[9S08QG8]
PROGRAMMING_ALGORITHM=0
DOTRIM=1
PRESERVE1_START=0
PRESERVE1_END=0
PRESERVE1_ACTIVE=0
PRESERVE2_START=0
PRESERVE2_END=0
PRESERVE2_ACTIVE=0
PRESERVE3_START=0
PRESERVE3_END=0
PRESERVE3_ACTIVE=0
PRESERVE_EEPROM=0
CUSTOM_TRIM=0
NGS_TRIM_OVERRIDE_REFERENCE_FREQUENCY=0
[SETTINGS]
MEMORYSTART1=96
MEMORYSTART2=0
DEFAULT_SOURCE_PATH=C:\Program Files (x86)\Freescale\CodeWarrior for Microcontrollers V6.3\prog
[CycleWin]
XTAL=4000000

51
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[Environment Variables]
GENPATH={Project}Sources;{Compiler}lib\hc08c\device\src;{Compiler}lib\hc08c\device\include;{Compiler}lib\hc08c\device\asm_include;{Compiler}lib\hc08c\src;{Compiler}lib\hc08c\include;{Compiler}lib\hc08c\lib
LIBPATH={Compiler}lib\hc08c\device\include;{Compiler}lib\hc08c\include
OBJPATH={Project}bin
TEXTPATH={Project}bin
ABSPATH={Project}bin
[HI-WAVE]
Target=HCS08OpenSourceBDM
Layout=C_layout.hwl
LoadDialogOptions=AUTOERASEANDFLASH RUNANDSTOPAFTERLOAD="main"
MainFrame=2,3,-1,-1,-1,-1,104,104,1544,857
TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806
AEFWarningDialog=FALSE
[HCS08 Open Source BDM]
COMSETTINGS=SETCOMM DRIVER NOPROTOCOL NOPERIODICAL
ISRDISABLEDSTEP=0
FLASHTRIMONLOAD=1
NV_PARAMETER_FILE=
NV_SAVE_WSP=0
NV_AUTO_ID=1
[HCS08 Open Source BDM_GDI_SETTINGS]
CMDFILE0=CMDFILE STARTUP ON ".\cmd\HCS08_OpenSourceBDM_startup.cmd"
CMDFILE1=CMDFILE RESET ON ".\cmd\HCS08_OpenSourceBDM_reset.cmd"
CMDFILE2=CMDFILE PRELOAD ON ".\cmd\HCS08_OpenSourceBDM_preload.cmd"
CMDFILE3=CMDFILE POSTLOAD ON ".\cmd\HCS08_OpenSourceBDM_postload.cmd"
CMDFILE4=CMDFILE UNSECURE ON ".\cmd\HCS08_OpenSourceBDM_Erase_Unsecure.cmd"
MCUID=0x1019
COMDEVICE=SETCOMM COMPORT LPT "OSBDM #1"
CMDFILE5=CMDFILE VPPON ON "vppon.cmd"
CMDFILE6=CMDFILE VPPOFF ON "vppoff.cmd"
CHIPSECURE=CHIPSECURE SETUP 0xFFBF 0x3 0x2
HCS08DBGMODULEADR=0x1810
DBG0=DBG GENERAL DISARM_ON PROTECT_OFF ANALYZE_ON STEPATRUN_ON
DBG1=DBG PREDEFINED SELECT 0
DBG2=DBG PREDEFINED DBGENGINE END STOP 0x0
DBG3=DBG USER 0x0 0x0
NV_PARAMETER_FILE=C:\Program Files (x86)\Freescale\CodeWarrior for Microcontrollers V6.3\prog\FPP\mcu1019.fpp
NV_SAVE_WSP=0
NV_AUTO_ID=1

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/******************************************************************************
FILE : start08.c
PURPOSE : 68HC08 standard startup code
LANGUAGE : ANSI-C / INLINE ASSEMBLER
----------------------------------------------------------------------------
HISTORY
22 oct 93 Created.
04/17/97 Also C++ constructors called in Init().
******************************************************************************/
/**********************************************************************/
/* NOTE: */
/* This version of the startup code assumes that main */
/* does never return (saving the 2 byte return address of _Startup on */
/* the stack). */
/**********************************************************************/
#define __NO_FLAGS_OFFSET /* we do not need the flags field in the startup data descriptor */
#define __NO_MAIN_OFFSET /* we do not need the main field in the startup data descriptor */
#include <start08.h>
#ifdef __cplusplus
#define __EXTERN_C extern "C"
#else
#define __EXTERN_C
#endif
__EXTERN_C extern void main(void); /* prototype of main function */
#include "non_bank.sgm"
/***************************************************************************/
/* Macros to control how the startup code handles the COP: */
/* #define _DO_FEED_COP_ : do feed the COP */
/* Without defining any of these, the startup code does NOT handle the COP */
/***************************************************************************/
/* __ONLY_INIT_SP define: */
/* This define selects an shorter version of the startup code */
/* which only loads the stack pointer and directly afterwards calls */
/* main. This version does however NOT initialize global variables */
/* (so this version is not ANSI compliant!). */
/***************************************************************************/
#if defined(_DO_FEED_COP_)
#define __FEED_COP_IN_HLI() } _FEED_COP(); __asm {
#else
#define __FEED_COP_IN_HLI() /* do nothing */
#endif
#ifndef __ONLY_INIT_SP
#pragma DATA_SEG FAR _STARTUP
struct _tagStartup _startupData; /* read-only:
_startupData is allocated in ROM and
initialized by the linker */
#pragma MESSAGE DISABLE C20001 /* Warning C20001: Different value of stack pointer depending on control-flow */
/* the function _COPY_L releases some bytes from the stack internally */
#if defined(__OPTIMIZE_FOR_SIZE__) || defined(_DO_FEED_COP_)
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
/*lint -esym(528, loadByte) inhibit warning about unreferenced loadByte function */
static void near loadByte(void) {
asm {
PSHH
PSHX
#ifdef __HCS08__
LDHX 5,SP
LDA 0,X
AIX #1
STHX 5,SP
#else
LDA 5,SP
PSHA
LDX 7,SP
PULH
LDA 0,X
AIX #1
STX 6,SP
PSHH
PULX
STX 5,SP
#endif
PULX
PULH
RTS
}
}
#endif /* defined(__OPTIMIZE_FOR_SIZE__) || defined(_DO_FEED_COP_) */
#ifdef __cplusplus
static void Call_Constructors(void) {
int i;
#ifdef __ELF_OBJECT_FILE_FORMAT__
i = (int)(_startupData.nofInitBodies - 1);
while (i >= 0) {
(&_startupData.initBodies->initFunc)[i](); /* call C++ constructors */
i--;
}
#else /* __ELF_OBJECT_FILE_FORMAT__ */
/* HIWARE object file format */
if (_startupData.mInits != NULL) {
_PFunc *fktPtr;
fktPtr = _startupData.mInits;
while(*fktPtr != NULL) {
(**fktPtr)(); /* call constructor */
fktPtr++;
}
}
#endif /* __ELF_OBJECT_FILE_FORMAT__ */
}
#endif
/*lint -esym(752,_COPY_L) inhibit message on function declared, but not used (it is used in HLI) */
__EXTERN_C extern void _COPY_L(void);
/* DESC: copy very large structures (>= 256 bytes) in 16-bit address space (stack incl.)
IN: TOS count, TOS(2) @dest, H:X @src
OUT:
WRITTEN: X,H */
#ifdef __ELF_OBJECT_FILE_FORMAT__
#define toCopyDownBegOffs 0
#else
#define toCopyDownBegOffs 2 /* for the hiware format, the toCopyDownBeg field is a long. Because the HC08 is big endian, we have to use an offset of 2 */
#endif
static void Init(void) {
/* purpose: 1) zero out RAM-areas where data is allocated
2) init run-time data
3) copy initialization data from ROM to RAM
*/
/*lint -esym(529,p,i) inhibit warning about symbols not used: it is used in HLI below */
int i;
int *far p;
asm {
ZeroOut:
LDA _startupData.nofZeroOuts:1 ; // nofZeroOuts
INCA
STA i:1 ; // i is counter for number of zero outs
LDA _startupData.nofZeroOuts:0 ; // nofZeroOuts
INCA
STA i:0
LDHX _startupData.pZeroOut ; // *pZeroOut
BRA Zero_5
Zero_3:
; // CLR i:1 is already 0
Zero_4:
; // { HX == _pZeroOut }
PSHX
PSHH
; // { nof bytes in (int)2,X }
; // { address in (int)0,X }
LDA 0,X
PSHA
LDA 2,X
INCA
STA p ; // p:0 is used for high byte of byte counter
LDA 3,X
LDX 1,X
PULH
INCA
BRA Zero_0
Zero_1:
; // CLRA A is already 0, so we do not have to clear it
Zero_2:
CLR 0,X
AIX #1
__FEED_COP_IN_HLI() ; // it's necessary to feed the COP in the inner loop for the fast COP timeout of some derivatives
Zero_0:
DBNZA Zero_2
Zero_6:
DBNZ p, Zero_1
PULH
PULX ; // restore *pZeroOut
AIX #4 ; // advance *pZeroOut
Zero_5:
DBNZ i:1, Zero_4
DBNZ i:0, Zero_3
CopyDown:
}
/* copy down */
/* _startupData.toCopyDownBeg ---> {nof(16) dstAddr(16) {bytes(8)}^nof} Zero(16) */
#if defined(__OPTIMIZE_FOR_SIZE__) || defined(_DO_FEED_COP_) /* for now: only -os version supports _DO_FEED_COP_ */
asm {
#ifdef __HCS08__
LDHX _startupData.toCopyDownBeg:toCopyDownBegOffs
PSHX
PSHH
#else
LDA _startupData.toCopyDownBeg:(1+toCopyDownBegOffs)
PSHA
LDA _startupData.toCopyDownBeg:(0+toCopyDownBegOffs)
PSHA
#endif
Loop0:
JSR loadByte ; // load high byte counter
TAX ; // save for compare
INCA
STA i
JSR loadByte ; // load low byte counter
INCA
STA i:1
DECA
BNE notfinished
CBEQX #0, finished
notfinished:
JSR loadByte ; // load high byte ptr
PSHA
PULH
JSR loadByte ; // load low byte ptr
TAX ; // HX is now destination pointer
BRA Loop1
Loop3:
Loop2:
__FEED_COP_IN_HLI()
JSR loadByte ; // load data byte
STA 0,X
AIX #1
Loop1:
DBNZ i:1, Loop2
DBNZ i:0, Loop3
BRA Loop0
finished:
AIS #2
}
#else /*defined(__OPTIMIZE_FOR_SIZE__) || defined(_DO_FEED_COP_) */
/* time optimized asm version. */
asm {
#ifdef __HCS08__
LDHX _startupData.toCopyDownBeg:toCopyDownBegOffs
#else
LDX _startupData.toCopyDownBeg:(0+toCopyDownBegOffs)
PSHX
PULH
LDX _startupData.toCopyDownBeg:(1+toCopyDownBegOffs)
#endif
next:
LDA 0,X ; // list is terminated by 2 zero bytes
ORA 1,X
BEQ copydone
PSHX ; // store current position
PSHH
LDA 3,X ; // psh dest low
PSHA
LDA 2,X ; // psh dest high
PSHA
LDA 1,X ; // psh cnt low
PSHA
LDA 0,X ; // psh cnt high
PSHA
AIX #4
JSR _COPY_L ; // copy one block
PULH
PULX
TXA
ADD 1,X ; // add low
PSHA
PSHH
PULA
ADC 0,X ; // add high
PSHA
PULH
PULX
AIX #4
BRA next
copydone:
}
#endif /* defined(__OPTIMIZE_FOR_SIZE__) || defined(_DO_FEED_COP_) */
/* FuncInits: for C++, this are the global constructors */
#ifdef __cplusplus
Call_Constructors();
#endif /* __cplusplus */
/* implement ROM libraries initialization here (see startup.c) */
}
#endif /* __ONLY_INIT_SP */
#pragma NO_EXIT
__EXTERN_C void _Startup(void) {
/* set the reset vector to _Startup in the linker parameter file (*.prm):
'VECTOR 0 _Startup'
purpose: 1) initialize the stack
2) initialize run-time, ...
initialize the RAM, copy down init data, etc (Init)
3) call main;
called from: _PRESTART-code generated by the Linker
*/
INIT_SP_FROM_STARTUP_DESC();
#ifndef __ONLY_INIT_SP
Init();
#endif
#ifndef __BANKED__
__asm JMP main; /* with a C style main(); we would push the return address on the stack wasting 2 RAM bytes */
#else
__asm CALL main;
#endif
}

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/*
* Note: This file is recreated by the project wizard whenever the MCU is
* changed and should not be edited by hand
*/
/* Include the derivative-specific header file */
#include <MC9S08QG8.h>
#define _Stop asm ( stop; )
/*!< Macro to enter stop modes, STOPE bit in SOPT1 register must be set prior to executing this macro */
#define _Wait asm ( wait; )
/*!< Macro to enter wait mode */

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#include <hidef.h> /* for EnableInterrupts macro */
#include "derivative.h" /* include peripheral declarations */
void main(void)
{
unsigned i;
/* Internal clock of 8MHz selected. */
ICSC2 = 0b01000000;
ICSC1 = 0x04;
SOPT1_COPE = 0; /* Disable Watchdog */
/* PTB configured as an output */
PTBDD = 0xFF;
for (;;)
{
i = 0;
{
while (i < 6513)
i++;
} // Boucle complète
PTBD = ~PTBD;
} /* loop forever */
}

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#define BP !PTAD_PTAD1
#define SW1 PTAD_PTAD2
#define SW2 PTAD_PTAD3
#define LED1 PTBD_PTBD0

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PROGRAM "E:\CITISE1\IUT\Info2\TP\Chap2\chapitre2\bin\Project.abs"
*********************************************************************************************
TARGET SECTION
---------------------------------------------------------------------------------------------
Processor : Freescale HC08
Memory Model: SMALL
File Format : ELF\DWARF 2.0
Linker : SmartLinker V-5.0.37 Build 9279, Oct 7 2009
*********************************************************************************************
FILE SECTION
---------------------------------------------------------------------------------------------
main.c.o Model: SMALL, Lang: ANSI-C
RTSHC08.C.o (ansiis.lib) Model: SMALL, Lang: ANSI-C
MC9S08QG8.C.o Model: SMALL, Lang: ANSI-C
Start08.c.o Model: SMALL, Lang: ANSI-C
*********************************************************************************************
STARTUP SECTION
---------------------------------------------------------------------------------------------
Entry point: 0xE07B (_Startup)
_startupData is allocated at 0xE084 and uses 6 Bytes
extern struct _tagStartup {
unsigned nofZeroOut 0
_Copy *toCopyDownBeg 0xE17A
} _startupData;
*********************************************************************************************
SECTION-ALLOCATION SECTION
Section Name Size Type From To Segment
---------------------------------------------------------------------------------------------
.init 132 R 0xE000 0xE083 ROM
.startData 14 R 0xE084 0xE091 ROM
.text 232 R 0xE092 0xE179 ROM
.copy 2 R 0xE17A 0xE17B ROM
.abs_section_0 1 N/I 0x0 0x0 .absSeg0
.abs_section_1 1 N/I 0x1 0x1 .absSeg1
.abs_section_2 1 N/I 0x2 0x2 .absSeg2
.abs_section_3 1 N/I 0x3 0x3 .absSeg3
.abs_section_c 1 N/I 0xC 0xC .absSeg4
.abs_section_d 1 N/I 0xD 0xD .absSeg5
.abs_section_e 1 N/I 0xE 0xE .absSeg6
.abs_section_f 1 N/I 0xF 0xF .absSeg7
.abs_section_10 1 N/I 0x10 0x10 .absSeg8
.abs_section_11 1 N/I 0x11 0x11 .absSeg9
.abs_section_16 1 N/I 0x16 0x16 .absSeg10
.abs_section_17 1 N/I 0x17 0x17 .absSeg11
.abs_section_1a 1 N/I 0x1A 0x1A .absSeg12
.abs_section_22 1 N/I 0x22 0x22 .absSeg13
.abs_section_23 1 N/I 0x23 0x23 .absSeg14
.abs_section_24 1 N/I 0x24 0x24 .absSeg15
.abs_section_25 1 N/I 0x25 0x25 .absSeg16
.abs_section_26 1 N/I 0x26 0x26 .absSeg17
.abs_section_27 1 N/I 0x27 0x27 .absSeg18
.abs_section_28 1 N/I 0x28 0x28 .absSeg19
.abs_section_29 1 N/I 0x29 0x29 .absSeg20
.abs_section_2a 1 N/I 0x2A 0x2A .absSeg21
.abs_section_2b 1 N/I 0x2B 0x2B .absSeg22
.abs_section_2d 1 N/I 0x2D 0x2D .absSeg23
.abs_section_30 1 N/I 0x30 0x30 .absSeg24
.abs_section_31 1 N/I 0x31 0x31 .absSeg25
.abs_section_32 1 N/I 0x32 0x32 .absSeg26
.abs_section_33 1 N/I 0x33 0x33 .absSeg27
.abs_section_34 1 N/I 0x34 0x34 .absSeg28
.abs_section_38 1 N/I 0x38 0x38 .absSeg29
.abs_section_39 1 N/I 0x39 0x39 .absSeg30
.abs_section_3a 1 N/I 0x3A 0x3A .absSeg31
.abs_section_3b 1 N/I 0x3B 0x3B .absSeg32
.abs_section_3c 1 N/I 0x3C 0x3C .absSeg33
.abs_section_3d 1 N/I 0x3D 0x3D .absSeg34
.abs_section_3e 1 N/I 0x3E 0x3E .absSeg35
.abs_section_3f 1 N/I 0x3F 0x3F .absSeg36
.abs_section_40 1 N/I 0x40 0x40 .absSeg37
.abs_section_45 1 N/I 0x45 0x45 .absSeg38
.abs_section_48 1 N/I 0x48 0x48 .absSeg39
.abs_section_1800 1 N/I 0x1800 0x1800 .absSeg40
.abs_section_1801 1 N/I 0x1801 0x1801 .absSeg41
.abs_section_1802 1 N/I 0x1802 0x1802 .absSeg42
.abs_section_1803 1 N/I 0x1803 0x1803 .absSeg43
.abs_section_1808 1 N/I 0x1808 0x1808 .absSeg44
.abs_section_1809 1 N/I 0x1809 0x1809 .absSeg45
.abs_section_180a 1 N/I 0x180A 0x180A .absSeg46
.abs_section_180c 1 N/I 0x180C 0x180C .absSeg47
.abs_section_1816 1 N/I 0x1816 0x1816 .absSeg48
.abs_section_1817 1 N/I 0x1817 0x1817 .absSeg49
.abs_section_1818 1 N/I 0x1818 0x1818 .absSeg50
.abs_section_1820 1 N/I 0x1820 0x1820 .absSeg51
.abs_section_1821 1 N/I 0x1821 0x1821 .absSeg52
.abs_section_1823 1 N/I 0x1823 0x1823 .absSeg53
.abs_section_1824 1 N/I 0x1824 0x1824 .absSeg54
.abs_section_1825 1 N/I 0x1825 0x1825 .absSeg55
.abs_section_1826 1 N/I 0x1826 0x1826 .absSeg56
.abs_section_1840 1 N/I 0x1840 0x1840 .absSeg57
.abs_section_1841 1 N/I 0x1841 0x1841 .absSeg58
.abs_section_1842 1 N/I 0x1842 0x1842 .absSeg59
.abs_section_1844 1 N/I 0x1844 0x1844 .absSeg60
.abs_section_1845 1 N/I 0x1845 0x1845 .absSeg61
.abs_section_1846 1 N/I 0x1846 0x1846 .absSeg62
.abs_section_12 2 N/I 0x12 0x13 .absSeg63
.abs_section_14 2 N/I 0x14 0x15 .absSeg64
.abs_section_20 2 N/I 0x20 0x21 .absSeg65
.abs_section_41 2 N/I 0x41 0x42 .absSeg66
.abs_section_43 2 N/I 0x43 0x44 .absSeg67
.abs_section_46 2 N/I 0x46 0x47 .absSeg68
.abs_section_49 2 N/I 0x49 0x4A .absSeg69
.abs_section_1806 2 N/I 0x1806 0x1807 .absSeg70
.abs_section_1810 2 N/I 0x1810 0x1811 .absSeg71
.abs_section_1812 2 N/I 0x1812 0x1813 .absSeg72
.abs_section_1814 2 N/I 0x1814 0x1815 .absSeg73
.stack 64 R/W 0x100 0x13F RAM
.vectSeg74_vect 2 R 0xFFFE 0xFFFF .vectSeg74
Summary of section sizes per section type:
READ_ONLY (R): 17E (dec: 382)
READ_WRITE (R/W): 40 (dec: 64)
NO_INIT (N/I): 55 (dec: 85)
*********************************************************************************************
VECTOR-ALLOCATION SECTION
Address InitValue InitFunction
---------------------------------------------------------------------------------------------
0xFFFE 0xE07B _Startup
*********************************************************************************************
OBJECT-ALLOCATION SECTION
Name Module Addr hSize dSize Ref Section RLIB
---------------------------------------------------------------------------------------------
MODULE: -- main.c.o --
- PROCEDURES:
main E092 31 49 1 .text
- VARIABLES:
MODULE: -- RTSHC08.C.o (ansiis.lib) --
- PROCEDURES:
_PUSH_ARGS_L E0C3 20 32 1 .text
_ENTER_UNARY_L E0E3 29 41 1 .text
_ENTER_BINARY_L_RC E10C 19 25 1 .text
_LCMP_k_rel_j E125 1F 31 1 .text
_LINC E144 16 22 1 .text
_LCMP_RC E15A 6 6 1 .text
_POP32 E160 1A 26 1 .text
- VARIABLES:
MODULE: -- MC9S08QG8.C.o --
- PROCEDURES:
- VARIABLES:
_PTAD 0 1 1 0 .abs_section_0
_PTADD 1 1 1 0 .abs_section_1
_PTBD 2 1 1 1 .abs_section_2
_PTBDD 3 1 1 1 .abs_section_3
_KBISC C 1 1 0 .abs_section_c
_KBIPE D 1 1 0 .abs_section_d
_KBIES E 1 1 0 .abs_section_e
_IRQSC F 1 1 0 .abs_section_f
_ADCSC1 10 1 1 0 .abs_section_10
_ADCSC2 11 1 1 0 .abs_section_11
_ADCCFG 16 1 1 0 .abs_section_16
_APCTL1 17 1 1 0 .abs_section_17
_ACMPSC 1A 1 1 0 .abs_section_1a
_SCIC1 22 1 1 0 .abs_section_22
_SCIC2 23 1 1 0 .abs_section_23
_SCIS1 24 1 1 0 .abs_section_24
_SCIS2 25 1 1 0 .abs_section_25
_SCIC3 26 1 1 0 .abs_section_26
_SCID 27 1 1 0 .abs_section_27
_SPIC1 28 1 1 0 .abs_section_28
_SPIC2 29 1 1 0 .abs_section_29
_SPIBR 2A 1 1 0 .abs_section_2a
_SPIS 2B 1 1 0 .abs_section_2b
_SPID 2D 1 1 0 .abs_section_2d
_IICA 30 1 1 0 .abs_section_30
_IICF 31 1 1 0 .abs_section_31
_IICC 32 1 1 0 .abs_section_32
_IICS 33 1 1 0 .abs_section_33
_IICD 34 1 1 0 .abs_section_34
_ICSC1 38 1 1 1 .abs_section_38
_ICSC2 39 1 1 1 .abs_section_39
_ICSTRM 3A 1 1 0 .abs_section_3a
_ICSSC 3B 1 1 0 .abs_section_3b
_MTIMSC 3C 1 1 0 .abs_section_3c
_MTIMCLK 3D 1 1 0 .abs_section_3d
_MTIMCNT 3E 1 1 0 .abs_section_3e
_MTIMMOD 3F 1 1 0 .abs_section_3f
_TPMSC 40 1 1 0 .abs_section_40
_TPMC0SC 45 1 1 0 .abs_section_45
_TPMC1SC 48 1 1 0 .abs_section_48
_SRS 1800 1 1 0 .abs_section_1800
_SBDFR 1801 1 1 0 .abs_section_1801
_SOPT1 1802 1 1 1 .abs_section_1802
_SOPT2 1803 1 1 0 .abs_section_1803
_SRTISC 1808 1 1 0 .abs_section_1808
_SPMSC1 1809 1 1 0 .abs_section_1809
_SPMSC2 180A 1 1 0 .abs_section_180a
_SPMSC3 180C 1 1 0 .abs_section_180c
_DBGC 1816 1 1 0 .abs_section_1816
_DBGT 1817 1 1 0 .abs_section_1817
_DBGS 1818 1 1 0 .abs_section_1818
_FCDIV 1820 1 1 0 .abs_section_1820
_FOPT 1821 1 1 0 .abs_section_1821
_FCNFG 1823 1 1 0 .abs_section_1823
_FPROT 1824 1 1 0 .abs_section_1824
_FSTAT 1825 1 1 0 .abs_section_1825
_FCMD 1826 1 1 0 .abs_section_1826
_PTAPE 1840 1 1 0 .abs_section_1840
_PTASE 1841 1 1 0 .abs_section_1841
_PTADS 1842 1 1 0 .abs_section_1842
_PTBPE 1844 1 1 0 .abs_section_1844
_PTBSE 1845 1 1 0 .abs_section_1845
_PTBDS 1846 1 1 0 .abs_section_1846
_ADCR 12 2 2 0 .abs_section_12
_ADCCV 14 2 2 0 .abs_section_14
_SCIBD 20 2 2 0 .abs_section_20
_TPMCNT 41 2 2 0 .abs_section_41
_TPMMOD 43 2 2 0 .abs_section_43
_TPMC0V 46 2 2 0 .abs_section_46
_TPMC1V 49 2 2 0 .abs_section_49
_SDID 1806 2 2 0 .abs_section_1806
_DBGCA 1810 2 2 0 .abs_section_1810
_DBGCB 1812 2 2 0 .abs_section_1812
_DBGF 1814 2 2 0 .abs_section_1814
MODULE: -- Start08.c.o --
- PROCEDURES:
loadByte E000 E 14 5 .init
Init E00E 6D 109 1 .init
_Startup E07B 9 9 0 .init
- VARIABLES:
_startupData E084 6 6 4 .startData
- LABELS:
__SEG_END_SSTACK 140 0 0 1
*********************************************************************************************
MODULE STATISTIC
Name Data Code Const
---------------------------------------------------------------------------------------------
main.c.o 0 49 0
RTSHC08.C.o (ansiis.lib) 0 183 0
MC9S08QG8.C.o 85 0 0
Start08.c.o 0 132 0
other 64 16 2
*********************************************************************************************
SECTION USE IN OBJECT-ALLOCATION SECTION
---------------------------------------------------------------------------------------------
SECTION: ".text"
main _PUSH_ARGS_L _ENTER_UNARY_L _ENTER_BINARY_L_RC _LCMP_k_rel_j _LINC
_LCMP_RC _POP32
SECTION: ".init"
loadByte Init _Startup
SECTION: ".abs_section_0"
_PTAD
SECTION: ".abs_section_1"
_PTADD
SECTION: ".abs_section_2"
_PTBD
SECTION: ".abs_section_3"
_PTBDD
SECTION: ".abs_section_c"
_KBISC
SECTION: ".abs_section_d"
_KBIPE
SECTION: ".abs_section_e"
_KBIES
SECTION: ".abs_section_f"
_IRQSC
SECTION: ".abs_section_10"
_ADCSC1
SECTION: ".abs_section_11"
_ADCSC2
SECTION: ".abs_section_16"
_ADCCFG
SECTION: ".abs_section_17"
_APCTL1
SECTION: ".abs_section_1a"
_ACMPSC
SECTION: ".abs_section_22"
_SCIC1
SECTION: ".abs_section_23"
_SCIC2
SECTION: ".abs_section_24"
_SCIS1
SECTION: ".abs_section_25"
_SCIS2
SECTION: ".abs_section_26"
_SCIC3
SECTION: ".abs_section_27"
_SCID
SECTION: ".abs_section_28"
_SPIC1
SECTION: ".abs_section_29"
_SPIC2
SECTION: ".abs_section_2a"
_SPIBR
SECTION: ".abs_section_2b"
_SPIS
SECTION: ".abs_section_2d"
_SPID
SECTION: ".abs_section_30"
_IICA
SECTION: ".abs_section_31"
_IICF
SECTION: ".abs_section_32"
_IICC
SECTION: ".abs_section_33"
_IICS
SECTION: ".abs_section_34"
_IICD
SECTION: ".abs_section_38"
_ICSC1
SECTION: ".abs_section_39"
_ICSC2
SECTION: ".abs_section_3a"
_ICSTRM
SECTION: ".abs_section_3b"
_ICSSC
SECTION: ".abs_section_3c"
_MTIMSC
SECTION: ".abs_section_3d"
_MTIMCLK
SECTION: ".abs_section_3e"
_MTIMCNT
SECTION: ".abs_section_3f"
_MTIMMOD
SECTION: ".abs_section_40"
_TPMSC
SECTION: ".abs_section_45"
_TPMC0SC
SECTION: ".abs_section_48"
_TPMC1SC
SECTION: ".abs_section_1800"
_SRS
SECTION: ".abs_section_1801"
_SBDFR
SECTION: ".abs_section_1802"
_SOPT1
SECTION: ".abs_section_1803"
_SOPT2
SECTION: ".abs_section_1808"
_SRTISC
SECTION: ".abs_section_1809"
_SPMSC1
SECTION: ".abs_section_180a"
_SPMSC2
SECTION: ".abs_section_180c"
_SPMSC3
SECTION: ".abs_section_1816"
_DBGC
SECTION: ".abs_section_1817"
_DBGT
SECTION: ".abs_section_1818"
_DBGS
SECTION: ".abs_section_1820"
_FCDIV
SECTION: ".abs_section_1821"
_FOPT
SECTION: ".abs_section_1823"
_FCNFG
SECTION: ".abs_section_1824"
_FPROT
SECTION: ".abs_section_1825"
_FSTAT
SECTION: ".abs_section_1826"
_FCMD
SECTION: ".abs_section_1840"
_PTAPE
SECTION: ".abs_section_1841"
_PTASE
SECTION: ".abs_section_1842"
_PTADS
SECTION: ".abs_section_1844"
_PTBPE
SECTION: ".abs_section_1845"
_PTBSE
SECTION: ".abs_section_1846"
_PTBDS
SECTION: ".abs_section_12"
_ADCR
SECTION: ".abs_section_14"
_ADCCV
SECTION: ".abs_section_20"
_SCIBD
SECTION: ".abs_section_41"
_TPMCNT
SECTION: ".abs_section_43"
_TPMMOD
SECTION: ".abs_section_46"
_TPMC0V
SECTION: ".abs_section_49"
_TPMC1V
SECTION: ".abs_section_1806"
_SDID
SECTION: ".abs_section_1810"
_DBGCA
SECTION: ".abs_section_1812"
_DBGCB
SECTION: ".abs_section_1814"
_DBGF
*********************************************************************************************
OBJECT LIST SORTED BY ADDRESS
Name Addr hSize dSize Ref Section RLIB
---------------------------------------------------------------------------------------------
_PTAD 0 1 1 0 .abs_section_0
_PTADD 1 1 1 0 .abs_section_1
_PTBD 2 1 1 1 .abs_section_2
_PTBDD 3 1 1 1 .abs_section_3
_KBISC C 1 1 0 .abs_section_c
_KBIPE D 1 1 0 .abs_section_d
_KBIES E 1 1 0 .abs_section_e
_IRQSC F 1 1 0 .abs_section_f
_ADCSC1 10 1 1 0 .abs_section_10
_ADCSC2 11 1 1 0 .abs_section_11
_ADCR 12 2 2 0 .abs_section_12
_ADCCV 14 2 2 0 .abs_section_14
_ADCCFG 16 1 1 0 .abs_section_16
_APCTL1 17 1 1 0 .abs_section_17
_ACMPSC 1A 1 1 0 .abs_section_1a
_SCIBD 20 2 2 0 .abs_section_20
_SCIC1 22 1 1 0 .abs_section_22
_SCIC2 23 1 1 0 .abs_section_23
_SCIS1 24 1 1 0 .abs_section_24
_SCIS2 25 1 1 0 .abs_section_25
_SCIC3 26 1 1 0 .abs_section_26
_SCID 27 1 1 0 .abs_section_27
_SPIC1 28 1 1 0 .abs_section_28
_SPIC2 29 1 1 0 .abs_section_29
_SPIBR 2A 1 1 0 .abs_section_2a
_SPIS 2B 1 1 0 .abs_section_2b
_SPID 2D 1 1 0 .abs_section_2d
_IICA 30 1 1 0 .abs_section_30
_IICF 31 1 1 0 .abs_section_31
_IICC 32 1 1 0 .abs_section_32
_IICS 33 1 1 0 .abs_section_33
_IICD 34 1 1 0 .abs_section_34
_ICSC1 38 1 1 1 .abs_section_38
_ICSC2 39 1 1 1 .abs_section_39
_ICSTRM 3A 1 1 0 .abs_section_3a
_ICSSC 3B 1 1 0 .abs_section_3b
_MTIMSC 3C 1 1 0 .abs_section_3c
_MTIMCLK 3D 1 1 0 .abs_section_3d
_MTIMCNT 3E 1 1 0 .abs_section_3e
_MTIMMOD 3F 1 1 0 .abs_section_3f
_TPMSC 40 1 1 0 .abs_section_40
_TPMCNT 41 2 2 0 .abs_section_41
_TPMMOD 43 2 2 0 .abs_section_43
_TPMC0SC 45 1 1 0 .abs_section_45
_TPMC0V 46 2 2 0 .abs_section_46
_TPMC1SC 48 1 1 0 .abs_section_48
_TPMC1V 49 2 2 0 .abs_section_49
_SRS 1800 1 1 0 .abs_section_1800
_SBDFR 1801 1 1 0 .abs_section_1801
_SOPT1 1802 1 1 1 .abs_section_1802
_SOPT2 1803 1 1 0 .abs_section_1803
_SDID 1806 2 2 0 .abs_section_1806
_SRTISC 1808 1 1 0 .abs_section_1808
_SPMSC1 1809 1 1 0 .abs_section_1809
_SPMSC2 180A 1 1 0 .abs_section_180a
_SPMSC3 180C 1 1 0 .abs_section_180c
_DBGCA 1810 2 2 0 .abs_section_1810
_DBGCB 1812 2 2 0 .abs_section_1812
_DBGF 1814 2 2 0 .abs_section_1814
_DBGC 1816 1 1 0 .abs_section_1816
_DBGT 1817 1 1 0 .abs_section_1817
_DBGS 1818 1 1 0 .abs_section_1818
_FCDIV 1820 1 1 0 .abs_section_1820
_FOPT 1821 1 1 0 .abs_section_1821
_FCNFG 1823 1 1 0 .abs_section_1823
_FPROT 1824 1 1 0 .abs_section_1824
_FSTAT 1825 1 1 0 .abs_section_1825
_FCMD 1826 1 1 0 .abs_section_1826
_PTAPE 1840 1 1 0 .abs_section_1840
_PTASE 1841 1 1 0 .abs_section_1841
_PTADS 1842 1 1 0 .abs_section_1842
_PTBPE 1844 1 1 0 .abs_section_1844
_PTBSE 1845 1 1 0 .abs_section_1845
_PTBDS 1846 1 1 0 .abs_section_1846
loadByte E000 E 14 5 .init
Init E00E 6D 109 1 .init
_Startup E07B 9 9 0 .init
main E092 31 49 1 .text
_PUSH_ARGS_L E0C3 20 32 1 .text
_ENTER_UNARY_L E0E3 29 41 1 .text
_ENTER_BINARY_L_RC E10C 19 25 1 .text
_LCMP_k_rel_j E125 1F 31 1 .text
_LINC E144 16 22 1 .text
_LCMP_RC E15A 6 6 1 .text
_POP32 E160 1A 26 1 .text
*********************************************************************************************
UNUSED-OBJECTS SECTION
---------------------------------------------------------------------------------------------
NOT USED PROCEDURES
RTSHC08.C.o (ansiis.lib):
_PUSH_ARGS_D _ENTER_UNARY_L64 _ENTER_UNARY_L64_4 _ENTER_BINARY_L
_ENTER_BINARY_L_LC _ENTER_BINARY_L64 _ENTER_BINARY_L64_LC
_ENTER_BINARY_L64_RC _IDIVMOD _SPLITSIGN _LADD_k_is_k_plus_j _k_is_k_plus_j_l
_k_is_k_plus_j_i _LSUB_k_is_k_minus_j _LAND_k_is_k_and_j _LOR_k_is_k_or_j
_LXOR_k_is_k_xor_j _LMUL_k_is_k_mul_j _LDIVMOD _NEG_L_HX _ABS_L_HX
_SPLITSIGN_L _LMODU_k_is_k_mod_j _LDIVU_k_is_k_div_j _LMODS_k_is_k_mod_j
_LDIVS_k_is_k_div_j _CMP24_k_rel_j _BMULS _BDIVS _BMODS _IMUL_STAR08
_IDIVS_STAR08 _IDIVU_STAR08 _IMODS_STAR08 _IMODU_STAR08 _IDIVU_8 _IMODU_8
_IASR _ILSR _ILSL _ICMP _LDEC _LNEG _LNOT _LADD _LADD_RC _LSUB _LSUB_LC
_LSUB_RC _LAND _LAND_RC _LOR _LOR_RC _LXOR _LXOR_RC _LMUL _LMUL_RC _LDIVS
_LDIVS_LC _LDIVS_RC _LDIVU _LDIVU_LC _LDIVU_RC _LMODS _LMODS_LC _LMODS_RC
_LMODU _LMODU_LC _LMODU_RC _LASR _LLSR _LLSL _LCMP _PUSH_ARGS_24
_ENTER_BINARY_24_RC _ENTER_BINARY_24 _CMP24 _CMP24_RC _COPY _COPY_L _POP64
_STORE32 _STORE64 _SEXT8_32 _SEXT16_32 _CALL_STAR08 _CALL_STAR08_FAR
_Jump_Table_Addr _Jump_Table_Offset _Jump_Table_Header_Addr
_Jump_Table_Header_Offset _Search_Table_16_Addr _Search_Table_16_Offset
_Search_Table_8_Addr _Search_Table_8_Offset _PUSH_CC _POP_CC
_CONV_FAR_TO_NEAR _CONV_FAR_TO_LINEAR _CONV_LINEAR_TO_FAR
NOT USED VARIABLES
RTSHC08.C.o (ansiis.lib):
_PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 errno
*********************************************************************************************
COPYDOWN SECTION
---------------------------------------------------------------------------------------------
------- ROM-ADDRESS: 0xE17A ---- SIZE 2 ---
Filling bytes inserted
0000
*********************************************************************************************
OBJECT-DEPENDENCIES SECTION
---------------------------------------------------------------------------------------------
Init USES _startupData loadByte
_Startup USES __SEG_END_SSTACK Init main
main USES _ICSC2 _ICSC1 _SOPT1 _PTBDD _LINC _POP32
_LCMP_RC _PTBD
_ENTER_BINARY_L_RC USES _PUSH_ARGS_L
_LINC USES _ENTER_UNARY_L
_LCMP_RC USES _ENTER_BINARY_L_RC _LCMP_k_rel_j
*********************************************************************************************
DEPENDENCY TREE
*********************************************************************************************
main and _Startup Group
|
+- main
| |
| +- _LINC
| | |
| | +- _ENTER_UNARY_L
| |
| +- _POP32
| |
| +- _LCMP_RC
| |
| +- _ENTER_BINARY_L_RC
| | |
| | +- _PUSH_ARGS_L
| |
| +- _LCMP_k_rel_j
|
+- _Startup
|
+- Init
| |
| +- loadByte
|
+- main (see above)
*********************************************************************************************
STATISTIC SECTION
---------------------------------------------------------------------------------------------
ExeFile:
--------
Number of blocks to be downloaded: 3
Total size of all blocks to be downloaded: 382

BIN
IUT/Info2/TP/Chap2/chapitre2/chapitre2.mcp Normal file
View File

Binary file not shown.

BIN
IUT/Info2/TP/Chap2/chapitre2/chapitre2_Data/CWSettingsWindows.stg Normal file
View File

Binary file not shown.

BIN
IUT/Info2/TP/Chap2/chapitre2/chapitre2_Data/Standard/ObjectCode/MC9S08QG8.C.o Normal file
View File

Binary file not shown.

BIN
IUT/Info2/TP/Chap2/chapitre2/chapitre2_Data/Standard/ObjectCode/Start08.c.o Normal file
View File

Binary file not shown.

BIN
IUT/Info2/TP/Chap2/chapitre2/chapitre2_Data/Standard/ObjectCode/main.c.o Normal file
View File

Binary file not shown.

BIN
IUT/Info2/TP/Chap2/chapitre2/chapitre2_Data/Standard/TargetDataWindows.tdt Normal file
View File

Binary file not shown.

1
IUT/Info2/TP/Chap2/chapitre2/cmd/HCS08_Full_Chip_Simulator_Postload.cmd Normal file
View File

@@ -0,0 +1 @@
// After load the commands written below will be executed

1
IUT/Info2/TP/Chap2/chapitre2/cmd/HCS08_Full_Chip_Simulator_Preload.cmd Normal file
View File

@@ -0,0 +1 @@
// Before load the commands written below will be executed

1
IUT/Info2/TP/Chap2/chapitre2/cmd/HCS08_Full_Chip_Simulator_Reset.cmd Normal file
View File

@@ -0,0 +1 @@
// After reset the commands written below will be executed

1
IUT/Info2/TP/Chap2/chapitre2/cmd/HCS08_Full_Chip_Simulator_Startup.cmd Normal file
View File

@@ -0,0 +1 @@
// At startup the commands written below will be executed

66
IUT/Info2/TP/Chap2/chapitre2/cmd/HCS08_OpenSourceBDM_Erase_Unsecure.cmd Normal file
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// ver 2.1 (16-Oct-06)
// HCS08 erasing + unsecuring command file:
// These commands mass erase the chip then program the security byte to 0xFE (unsecured state + backdoor key mechanism enabled).
// Evaluate the clock divider to set in FCDIV register:
DEFINEVALUEDLG "Information required to unsecure the device" "FCDIV" 19 "To unsecure the device, the command script needs \nthe correct value for FCDIV onchip register.\n\nIf the bus frequency is less than 10 MHz, the value\nto store in FCDIV is equal to:\n \"bus frequency (kHz) / 175\"\n\nIf the bus frequency is higher than 10 MHz, the value\nto store in FCDIV is equal to:\n \" bus frequency (kHz) / 1400 + 64\"\n(+64 (0x40) is to set PRDIV8 flag)\n\nDatasheet proposed values:\n\nbus frequency\t\tFCDIV value (decimal)\n\n 20 \tMHz\t\t76\n 10 \tMHz\t\t49\n 8 \tMHz\t\t39\n 4 \tMHz\t\t19\n 2 \tMHz\t\t9\n 1 \tMHz\t\t4\n200 \tkHz\t\t0\n150 \tkHz\t\t0\n"
// An average programming clock of 175 kHz is chosen.
// If the bus frequency is less than 10 MHz, the value to store
// in FCDIV is equal to " bus frequency (kHz) / 175 ".
// If the bus frequency is higher than 10 MHz, the value to store
// in FCDIV is equal to " bus frequency (kHz) / 1400 + 0x40 (to set PRDIV8 flag)".
// Datasheet proposed values:
//
// bus frequency FCDIV value (decimal)
//
// 20 MHz 76
// 10 MHz 49
// 8 MHz 39
// 4 MHz 19
// 2 MHz 9
// 1 MHz 4
// 200 kHz 0
// 150 kHz 0
FLASH release
wb 0x1802 3 // disable COP clearing SIMOPT register + set BKGDPE and RSTPE (when available)
wb 0x1825 0x30 // clear FPVIOL and FACCERR in FSTAT register
wb 0x1824 0xff // remove all flash protections clearing FPROT register
wb 0x1820 FCDIV // set clock divider FCDIV register
// Please see below to find how to evaluate this constant value.
//mass erase flash
wb 0x1825 0x30 // clear FPVIOL and FACCERR in FSTAT register
wb 0xff80 0 // (dummy) write to flash array to buffer address and data
wb 0x1826 0x41 // write MASS ERASE command in FCMD register
wb 0x1825 0x80 // set FCBEF in FSTAT register to execute the command
wait 20
//blankcheck flash
wb 0x1825 0x30 // clear FPVIOL and FACCERR in FSTAT register
wb 0xff80 0 // (dummy) write to flash array to buffer address and data
wb 0x1826 0x5 // write BLANK CHECK command in FCMD register
wb 0x1825 0x80 // set FCBEF in FSTAT register to execute the command
wait 20
//reprogram Security byte to Unsecure state
wb 0x1820 FCDIV // set clock divider FCDIV register
wb 0x1825 0x30 // clear FPVIOL and FACCERR in FSTAT register
wb 0xffbf 0xfe // write NVFEOPT register in flash array to UNSECURED state with Backdoor Key Mechanism enabled
wb 0x1826 0x20 // write BYTE PROGRAM command in FCMD register
wb 0x1825 0x80 // set FCBEF in FSTAT register to execute the command
wait 10
DMM RELEASECACHES // release memory data caches
reset
undef FCDIV

1
IUT/Info2/TP/Chap2/chapitre2/cmd/HCS08_OpenSourceBDM_Postload.cmd Normal file
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// After load the commands written below will be executed

1
IUT/Info2/TP/Chap2/chapitre2/cmd/HCS08_OpenSourceBDM_Preload.cmd Normal file
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// Before load the commands written below will be executed

1
IUT/Info2/TP/Chap2/chapitre2/cmd/HCS08_OpenSourceBDM_Reset.cmd Normal file
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// After reset the commands written below will be executed

1
IUT/Info2/TP/Chap2/chapitre2/cmd/HCS08_OpenSourceBDM_Startup.cmd Normal file
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// At startup the commands written below will be executed

32
IUT/Info2/TP/Chap2/chapitre2/prm/Project.prm Normal file
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/* This is a linker parameter file for the mc9s08qg8 */
NAMES END /* CodeWarrior will pass all the needed files to the linker by command line. But here you may add your own files too. */
SEGMENTS /* Here all RAM/ROM areas of the device are listed. Used in PLACEMENT below. */
Z_RAM = READ_WRITE 0x0060 TO 0x00FF;
RAM = READ_WRITE 0x0100 TO 0x025F;
ROM = READ_ONLY 0xE000 TO 0xFFAD;
ROM1 = READ_ONLY 0xFFC0 TO 0xFFCF;
/* INTVECTS = READ_ONLY 0xFFD0 TO 0xFFFF; Reserved for Interrupt Vectors */
END
PLACEMENT /* Here all predefined and user segments are placed into the SEGMENTS defined above. */
DEFAULT_RAM, /* non-zero page variables */
INTO RAM;
_PRESTART, /* startup code */
STARTUP, /* startup data structures */
ROM_VAR, /* constant variables */
STRINGS, /* string literals */
VIRTUAL_TABLE_SEGMENT, /* C++ virtual table segment */
DEFAULT_ROM,
COPY /* copy down information: how to initialize variables */
INTO ROM; /* ,ROM1: To use "ROM1" as well, pass the option -OnB=b to the compiler */
_DATA_ZEROPAGE, /* zero page variables */
MY_ZEROPAGE INTO Z_RAM;
END
STACKSIZE 0x40
VECTOR 0 _Startup /* Reset vector: this is the default entry point for an application. */

9
IUT/Info2/TP/Chap2/chapitre2/prm/burner.bbl Normal file
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OPENFILE "%ABS_FILE%.s19"
format=motorola
busWidth=1
origin=0
len=0x1000000
destination=0
SRECORD=Sx
SENDBYTE 1 "%ABS_FILE%"
CLOSE

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